1. Field of the Invention
The present invention relates to a current buffer circuit and, more particularly, to a current buffer circuit comprising bipolar transistors.
2. Description of the Prior Art
A current buffer circuit is used to drive a heavy load in response to a signal supplied from a circuit having a low driving capability such as an internal circuit. That is, the current buffer circuit is inserted between the internal circuit and the load and responds to the signal from the internal circuit to drive the load with a large current ability and thus a lower impedance. The current buffer circuit is therefore also referred to as an impedance converter circuit.
Since the current buffer circuit is required to have the above mentioned purposes, it is constituted of a so-called push-pull circuit employing a PNP transistor and an NPN transistor each of an emitter-follower type.
Referring to FIG. 5, there is a circuit diagram of a prior art current buffer circuit 50 which is disclosed in Japanese Laid-Open Patent Application No. sho64-72606. This circuit includes an input terminal 11 is connected in common to the bases of a PNP transistor 7 and an NPN transistor 8, a resistor 29 connected between a positive power supply terminal 9 and the emitter of the PNP transistor 7, and a resistor 30 connected between a negative power supply terminal 10 and the emitter of the PNP transistor 8. This circuit 50 further includes an NPN transistor 3, resistors 5 and 6, and an NPN transistor 4 which are connected in series between the positive power supply terminal 9 and the negative power supply terminal 10. The node between the resistors 5 and 6 is connected to an output terminal 12 to which a load indicated by a capacitor 19 to be driven is connected. The NPN transistor 3 and the PNP transistor 4 have their bases connected to the emitter of the PNP transistor 7 and the emitter of the NPN transistor 8, respectively.
The emitter of the PNP transistor 7 has a level higher than that at the input terminal 11 by the forward base-emitter voltage (Vf), while the emitter of the NPN transistor 8 has a level lower than that at the input terminal 11 by Vf. In addition, the emitter of the NPN transistor 3 has a level lower than that at the emitter of the PNP transistor 7 by Vf, while the emitter of the PNP transistor 4 has a level higher than that at the emitter of the NPN transistor 8 by Vf. Therefore, a level equal to that of the input signal input at the input terminal 11 appears at the output terminal 12 as an output signal. The rise in the level of the input signal increases the base voltage of the NPN transistor 3, and decreases that of the PNP transistor 4 so that the level at the output terminal 12 also rises to the high level. On the contrary, a drop in the level at the input terminal increases the base voltage of the PNP transistor 4, and decreases that of the NPN transistor 3 so that the level at the output terminal 12 also drops and changes to the low level.
However, because the PNP transistor 4 has a current gain lower than that of the transistor 3, time required to decrease the voltage level at the output terminal 12 becomes longer than the time required to increase the voltage level at the output terminal 12. As the load 19 becomes heavier, the delay in changing to the low level at the output terminal 12 becomes significant.